1. Field of the Invention
The present invention relates to a delay circuit that includes a ferroelectric capacitor.
2. Related Art
A conventional delay circuit is disclosed in Japanese Unexamined Patent Publication No. 9-259590. The conventional delay circuit delays a signal by having a ferroelectric capacitor as a capacitance coupled to a propagation path of the signal
However, in the conventional delay circuit, there is a problem in that the delay circuits have wide variation in their delay times due to variations in their manufacturing process. For example, the delay time is defined as the time it takes an electric potential of a path to which the capacitor is coupled to exceed a threshold voltage of a transistor in the next circuit coupled to the path. The threshold voltage of transistors widely varies depending on variations in the manufacturing process. Accordingly, the delay circuits have a wide variation in delay times.
Furthermore, when the conventional delay circuit is applied to a ferroelectric memory device and the like, there is a problem in that a malfunction could occur since its operation timing could be off due to the variation in the delay time.
The present invention has been developed in consideration of the above-mentioned problem, and intended to provide a delay circuit that can solve the above-mentioned problems, a ferroelectric memory device and electronic equipment.